Integrated circuits are manufactured by forming a sequence of patterned layers. One process that may be used in the manufacture of integrated circuits is a chemical mechanical polishing (CMP) process. A chemical mechanical polishing process uses chemical and physical interactions between a polishing system and the surface of a substrate (e.g., a wafer) to improve the planarity of the surface.
One concern in a CMP process is that the wafer be polished uniformly across its surface, so that the desired degree of planarity is obtained. However, areas of the substrate that have more features generally polish at different rates than areas having fewer features.
In order to reduce polishing non-uniformity, special features called “dummification” features may be added. FIG. 1 shows a dummification lattice 110 including regularly arrayed square features 120. These features may provide more uniform feature density but may not be needed for the actual circuit design. Dummification therefore may improve the uniformity of a CMP process. For example, the CMP process may be improved by more closely matching the density of the dummification area with its surroundings. However, features 110 may prove problematic when used near alignment features.
Alignment features are generally sets of parallel lines that are used by the lithography system to determine the proper alignment to a previous layer, so that a new layer may be patterned with the correct spatial relationship to previously patterned layers. The alignment features are detected using either bright field (video) alignment, or dark field (diffraction) alignment. With either of these schemes, features positioned near alignment features (such as dummification features 110) can interact with the alignment light and prevent proper detection of the alignment features. As a result, dummification is generally omitted in regions near alignment features.
Like reference symbols in the various drawings indicate like elements.